(1) Field of the Invention
The invention relates to the manufacture of highly dense integrated circuits and more particularly to the reduction and elimination of electrostatic charge buildup at the device during manufacture in, for example, plasma etching or the like process steps.
(2) Description of the Prior Art
In the manufacture of highly dense integrated circuits using Metal Oxide Semiconductor (MOS) technology with multiple metal layers, electrical charge may build up at the device gate oxide during plasma processing. The charge accumulates on floating polysilicon and metal layers electrically connected to the gate oxide. Interconnection metal lines act as "antennas", amplifying the charging effect and leading to trapped charges at the gate oxide. These trapped charges can cause yield loss and reliability failures.
Workers in the field have verified this problem experimentally. Shone et al in "Gate Oxide Charging and Its Elimination for Metal Antenna Capacitor and Transistor in VLSI CMOS Double Layer Metal Technology" (published in "Symposium on VLSI Technology, pp. 73-74 in Jun., 1988) verified the antenna effect experimentally. They found that the double metal layer technologies worsened the effect by the ratio of the antenna area to the gate oxide area. The worst degradation of gate oxide occurred during oxynitride deposition, however other plasma processing is also believed to lead to trapped charges at the gate oxide.